IP-Cores / VHDL

My first IP-Core is a Advanced Encryption Standard (AES) Core with generics to configure the keylength (128, 192, or 256 Bits) an optional decryption datapath, also configurable with generics and an Altera Avalon-MM Slave Interface. I even wrote a documentation for this (WOW) I hope it is useful for you – if you have any comments or bugreports, please let me know.
You can download the Documentation here and the full Avalon-MM AES slave HDL source.
The whole project is licensed under a modified BSD license. I want as many people as possible to use this core. If you use it, please let me know so I can tell my girlfriend I am not wasting my time but helping humanity. Keep in mind – I am not liable for any damage the code might cause…..

UPDATE: I decided to publish this project at www.opencores.org. you will find the latest development branch there.


    • Christian on 2011-10-27 at 18:18

    Thanks for publishing your work!

    We are on the way to exchange the Altera specific sboxM4k part with Xilinx memory.
    Of course we are looking forward to the first functional tests of the module.

    • ruschi on 2011-10-28 at 14:53

    Hi Christian,
    make sure you use the source code & documentation from opencores.org.
    Please check if current versions of Xilinx ISE are now capable of synthesizing the 192 Bit version. I recall there is the problem of a division by 6 which ISE did not synthezise.
    Feel free to make changes needed – after all its BSD licensed.

Leave a Reply