Configurable AES IP Core with Avalon interface

My first successful open source project - Synthesizable Core in VHDL

My first IP-Core is a Advanced Encryption Standard (AES) Core with generics to configure the keylength (128, 192, or 256 Bits) an optional decryption datapath, also configurable with generics and an (optional) Altera Avalon-MM Slave Interface. I even wrote a documentation for this (WOW) I hope it is useful for you if you have any comments or bugreports, please let me know.

The core can be synthesized and I have run it successfully on a Altera Cyclone II EP2C35 FPGA. (using A HPE Mini AC II - Cyclone II board) I also created a SOC project with a NIOS2 Core running a C-testbench that uses the AES Core.

You can download the Documentation here and the full Avalon-MM AES slave VHDL source. The whole project is licensed under a modified BSD license. I want as many people as possible to use this core. If you use it, please let me know so I can tell my girlfriend I am not wasting my time but helping humanity. Keep in mind I am not liable for any damage the code might cause….

I am particularly proud of the datasheet

UPDATE: I decided to publish this project at,avs_aes. you will find the latest development branch there.

Actually I am quite pleased how many people are using the core and have sent me a “thank you email” :)

TODO: Move it to github since opencores seems dead…